1. Field of the Invention
Generally, the present disclosure relates to microstructures, such as advanced integrated circuits, and, more particularly, to metallization systems comprising sophisticated dielectric and conductive materials.
2. Description of the Related Art
In the fabrication of modern microstructures, such as integrated circuits, there is a continuous drive to steadily reduce the feature sizes of microstructure elements, thereby enhancing the functionality of these structures. For instance, in modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby increasing performance of these circuits in terms of speed and/or power consumption and/or diversity of functions. As the size of individual circuit elements is reduced with every new circuit generation, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect lines are also reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per unit die area, as typically the number of interconnections required increases more rapidly than the number of circuit elements. Thus, usually, a plurality of stacked “wiring” layers, also referred to as metallization layers, are provided, wherein individual metal lines of one metallization layer are connected to individual metal lines of an overlying or underlying metallization layer by so-called vias. Despite the provision of a plurality of metallization layers, reduced dimensions of the interconnect lines are necessary to comply with the enormous complexity of, for instance, modern CPUs, memory chips, ASICs (application specific ICs) and the like.
Advanced integrated circuits, including transistor elements having a critical dimension of 0.05 μm and even less, may, therefore, typically be operated at significantly increased current densities of up to several kA per cm2 in the individual interconnect structures, despite the provision of a relatively large number of metallization layers, owing to the significant number of circuit elements per unit area. Consequently, well-established materials, such as aluminum, are being replaced by copper and copper alloys, a material with significantly lower electrical resistivity and improved resistance to electromigration even at considerably higher current densities compared to aluminum. The introduction of copper into the fabrication of microstructures and integrated circuits comes along with a plurality of severe problems residing in copper's characteristic to readily diffuse in silicon dioxide and a plurality of low-k dielectric materials, which are typically used in combination with copper in order to reduce the parasitic capacitance within complex metallization layers. In order to provide the necessary adhesion and to avoid the undesired diffusion of copper atoms into sensitive device regions, it is, therefore, usually necessary to provide a barrier layer between the copper and the dielectric material in which the copper-based interconnect structures are embedded. Although silicon nitride is a dielectric material that effectively prevents the diffusion of copper atoms, selecting silicon nitride as an interlayer dielectric material is less then desirable, since silicon nitride exhibits a moderately high permittivity, thereby increasing the parasitic capacitance of neighboring copper lines, which may result in non-tolerable signal propagation delays. Hence, a thin conductive barrier layer that also imparts the required mechanical stability to the copper is usually formed so as to separate the bulk copper from the surrounding dielectric material, thereby reducing copper diffusion into the dielectric materials and also reducing the diffusion of unwanted species, such as oxygen, fluorine, and the like, into the copper. Furthermore, the conductive barrier layers may also provide highly stable interfaces with the copper, thereby reducing the probability for significant material transport at the interface, which is typically a critical region in view of increased diffusion paths that may facilitate current-induced material diffusion. Currently, tantalum, titanium, tungsten and their compounds, with nitrogen and silicon and the like, are preferred candidates for a conductive barrier layer, wherein the barrier layer may comprise two or more sub-layers of different composition to meet the requirements in terms of diffusion suppressing and adhesion properties.
Another characteristic of copper significantly distinguishing it from aluminum is the fact that copper may not be readily deposited in larger amounts by chemical and physical vapor deposition techniques, thereby requiring a process strategy that is commonly referred to as the damascene or inlaid technique. In the damascene process, first, a dielectric layer is formed which is then patterned to include trenches and/or vias which are subsequently filled with copper, wherein, as previously noted, prior to filling in the copper, a conductive barrier layer is formed on sidewalls of the trenches and vias. The deposition of the bulk copper material into the trenches and vias is usually accomplished by wet chemical deposition processes, such as electroplating and electroless plating, thereby requiring the reliable filling of vias with an aspect ratio of 5 and more with a diameter of 0.3 μm or even less, in combination with trenches having a width ranging from 0.1 μm to several μm. Electrochemical deposition processes for copper are well established in the field of electronic circuit board fabrication. However, for the dimensions of the metal regions in semiconductor devices, the void-free filling of high aspect ratio vias is an extremely complex and challenging task, wherein the characteristics of the finally obtained copper-based interconnect structure significantly depend on process parameters, materials and geometry of the structure of interest. Since the geometry of interconnect structures is substantially determined by the design requirements and may, therefore, not be significantly altered for a given microstructure, it is of great importance to estimate and control the impact of materials, such as conductive and non-conductive barrier layers, the copper microstructure and the like, and their mutual interaction on the characteristics of the interconnect structure as a whole so as to insure both high yield and the required product reliability. In particular, it is important to identify, monitor and reduce degradation and failure mechanisms in metallization systems for various configurations so as to maintain device reliability for every new device generation or technology node.
Accordingly, a great deal of effort is being made in investigating the degradation of copper interconnects, especially in combination with low-k dielectric materials or ultra low-k (ULK) materials having a relative permittivity of 3.0 or even less, in order to find new materials and process strategies for forming copper-based lines and vias with a low overall permittivity.
One failure mechanism, which is believed to significantly contribute to a premature device failure, is the electromigration-induced material transport, particularly along an interface formed between the copper and a dielectric cap layer, which may be provided after filling in the copper material in the trenches and via openings, the sidewalls of which are coated by the conductive barrier materials. In addition to maintaining copper integrity, the dielectric cap layer may usually act as an etch stop layer during the formation of the via openings in the interlayer dielectric. Frequently used materials are, for example, silicon nitride and nitrogen-containing silicon carbide, which exhibit a moderately high etch selectivity to typically employed interlayer dielectrics, such as a plurality of low-k dielectric materials, and also suppress the diffusion of copper into the interlayer dielectric. Recent research results seem to indicate, however, that the interface formed between the copper and dielectric cap layer is a major diffusion path for material transport during operation of the metal interconnect.
Consequently, a plurality of alternatives have been developed in an attempt to enhance the interface characteristics between the copper and the cap layer having the capability of reliably confining the copper and maintaining its integrity. For example, it has been proposed to selectively provide conductive materials on top of the copper-containing region, which may exhibit superior electromigration performance while not unduly reducing the overall resistance of the corresponding metal line. For instance, various alloys, such as a compound of cobalt/tungsten/phosphorous (CoWP), a compound of nickel/molybdenum/phosphorous (NiMoP) and the like, have proven to be promising candidates for conductive cap layers, which may significantly reduce electromigration effects within a corresponding metal line. Although these compounds provide superior electromigration performance and may be implemented into the overall process flow for manufacturing complex metallization systems, since these compounds may be efficiently deposited on the basis of selective electrochemical deposition recipes, it turns out, however, that severe defects may be observed in metallization systems including copper lines with a conductive cap layer. For example, increased leakage currents and dielectric breakdown may occur in such devices compared to devices having a metallization system based on a dielectric cap layer.
In addition, during operation of the device, a reduced time to dielectric breakdown may be observed in sophisticated metallization systems, wherein it is believed that a dominant source of the premature dielectric breakdown may represent the interface between the dielectric materials of two subsequent metallization layers in closely spaced metal lines, as will be explained with reference to FIG. 1a. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101, in and above which may be formed circuit elements, such as transistors and the like, as required by the overall circuit configuration of the semiconductor device 100. As previously indicated, the continuous shrinkage of the critical feature sizes, which may currently be at approximately 50 nm and less, requires a corresponding adaptation of the feature sizes of metal lines and vias in a metallization system 130 of the device 100. In the example shown in FIG. 1a, the metallization system 130 may comprise, in the manufacturing stage shown, a metallization layer 110 in a substantially complete state and a metallization layer 120 prior to patterning the corresponding dielectric material contained therein. The metallization layer 110 may comprise a dielectric material 111, such as a low-k dielectric material, and a plurality of metal lines 112, which may typically include a highly conductive metal 112A, such as copper, in combination with a conductive barrier material 112B, such as tantalum, tantalum nitride and the like. Furthermore, with respect to enhanced copper confinement and electromigration behavior, frequently, a conductive cap layer 113 may be formed on a top surface 112S of the metal region 112. As previously explained, a plurality of alloys may be used, which may have a moderately low resistivity while at the same time providing a strong interface with the surface 112S, which may, therefore, result in a reduced degree of current-induced material diffusion, as explained above. Typically, the metal lines 112 have a certain degree of tapering so that the critical dimension 112W in the vicinity of the top surface 112S may be greater compared to the corresponding critical width 112W at the bottom of the metal lines 112. Consequently, the distance 112D between neighboring closely spaced metal lines is shortest at an interface 111S of the dielectric material 111 with a subsequent dielectric material 122, which may be considered as a dielectric material of the subsequent metallization layer 120 or which may be considered as a cap or cover layer of the dielectric material 111. At any rate, the dielectric materials 122, 111 may typically differ in material composition so that diffusion paths for any contaminants, such as metal residues and the like, may preferably take place at the interface 111S. Furthermore, a further dielectric material 121, such as a low-k dielectric material and the like, may be formed on the dielectric layer 122.
Typically, the semiconductor device 100 as shown in FIG. 1a may be formed on the basis of the following process techniques. After fabricating any circuit elements in and above the substrate 101 based on well-established techniques according to specific design rules, which may require critical dimensions of 50 nm and significantly less for circuit elements, such as transistors and the like, an appropriate contact structure (not shown) may be formed so as to connect the corresponding circuit elements with the metallization system 130. Thereafter, the metallization system 130 may be formed, wherein the number and the configuration of the individual metallization layers 110, 120 may depend on the complexity and design criteria of the circuit provided by the circuit elements in the device level, as previously explained. For example, the metallization layer 110 including the metal lines 112 may be formed by depositing the dielectric material 111, which may represent a material of reduced permittivity, by any appropriate deposition technique, such as plasma enhanced chemical vapor deposition (CVD), spin-on techniques and the like. Thereafter, an appropriate etch mask may be formed on the basis of lithography, wherein hard mask materials may be used, if required, in order to define the lateral dimension 112W and the spacing 112D between adjacent metal lines 112. Thereafter, an anisotropic etch process may be performed on the basis of well-established recipes, during which a certain degree of tapering may be created so that, typically, the width 112W and the spacing 112D may have to be selected as large as is compatible with the overall design rules for a given high density of the metal lines 112. After the etch process and removal of the corresponding etch mask, the barrier material 112B may be formed, for instance, by sputter deposition and the like, followed by the filling in of the copper material, which may typically be accomplished by electrochemical deposition techniques. Thereafter, excess material of the copper fill material and of the conductive barrier layer 112B may be removed, wherein, typically, chemical mechanical polishing (CMP) techniques may be used. Consequently, during a final phase of a corresponding polishing sequence, copper material, barrier material and material of the dielectric layer 111 may be exposed to the polishing ambient, which may result in a certain degree of “copper contamination” of the surface 111S of the dielectric material 111. Although highly efficient cleaning processes may be performed in a later manufacturing stage, nevertheless, the presence of even minute copper residues may contribute to a reduced dielectric strength, in particular at the interface 111S, at which also the distance between neighboring metal lines 112 may be shortest. The situation may even become more critical in semiconductor devices in which the metal-containing cap material 113 may be provided. For this purpose, typically, a further electrochemical deposition process, frequently an electroless process, may be performed to selectively deposit the desired conductive cap material 113 on the surface portions 112S. During this process, exposed surface areas of the dielectric material 111 may also come into contact with electrolyte solutions comprising metal atoms which may also diffuse into the dielectric material to a certain degree. Thus, cleaning processes may be performed after the electroless deposition process to remove contaminants, wherein, however, minute metal residues may still remain from preceding chemical mechanical polishing of the copper material and the subsequent electroless deposition of the conductive cap material 113. Thereafter, the dielectric material 122 may be deposited, for instance by plasma enhanced CVD techniques, wherein the material 122 may act as an etch stop material during the patterning of the dielectric material 121 of the metallization layer 120. For example, silicon carbide, nitrogen-containing silicon carbide and the like may frequently be used as appropriate etch stop materials. However, due to a specific mismatch in material composition and molecular structure between the materials 122 and the dielectric material 111, the interface 111S may represent a diffusion path for metal residues which may result in an even further reduced dielectric strength upon operating the device 100, in which, typically, repeatedly moderately high temperatures may be created within the metallization system 130.
The dielectric material 121 may be deposited and may be subsequently patterned by using the layer 122 as a stop material, wherein vias and metal lines may be subsequently formed in the metallization layer 120.
Thus, the close proximity of the metal lines 112, in particular at the interface 112S, may provide increased electrical fields upon operation of the device 100, which may even become more critical due to the less stable interface 111S and the presence of even minute metal residues, for instance, in the form of copper or material of the conductive cap layer 113. Therefore, premature failure, that is, dielectric breakdown, may be observed in metallization levels of critical semiconductor devices.
For this reason, great efforts are being made in determining failures in the metallization systems and trying to locate corresponding reasons in the highly complex manufacturing flow and corresponding materials used therein. To this end, appropriately configured test structures are typically provided in the semiconductor devices, which may then be examined under predefined stress conditions, such as elevated temperatures, moderately high voltages and the like, in order to detect any weaknesses in the metallization system and the associated manufacturing techniques.
FIG. 1b schematically illustrates a top view of a typical test structure, which may represent a portion of a semiconductor device, such as the device 100, as previously described. The test structure 150 is typically provided as a portion of the metallization system, for instance as a portion of the metallization layer 110, as previously described. For example, the test structure 150 may be fabricated along with actual device features in the metallization layer 110, however, in dedicated device areas such as scribe lanes and the like, or even within the die area of actual semiconductor devices. In other cases, the test structures 150 may be formed on dedicated die areas or even test substrates, depending on the overall manufacturing strategy. The test structure 150 may thus comprise metal lines 112, which may have a similar configuration as previously described with reference to FIG. 1a. However, the metal lines 112 may not necessarily represent functional entities but may have an appropriate configuration, for instance with respect to the distance of two adjacent metal lines and the corresponding lateral dimensions thereof in order to provide information on the actual dielectric characteristics in the remaining metallization layer 110 formed above the actual device regions. For example, the line width and the spacing, as well as the configuration, may be substantially identical as in critical areas of the metallization layer 110 when actual device features are considered. In other cases, any other appropriate configuration may be realized, for instance, in view of determining minimum required distances with respect to a given manufacturing sequence so as to evaluate any technology inherent limitations and the like. Consequently, based on the test structure 150, the dielectric characteristics of the metallization layer 110 may be evaluated, for instance, in view of reliability with respect to a premature failure, as is also explained above in more detail. To this end, the test structure 150 may be exposed to certain stress conditions, indicated by 151, such as elevated temperature, humidity, mechanical stress and the like, while also a corresponding voltage may be applied across the test structure 150. For this purpose, an appropriate interconnect structure 130, which is merely schematically illustrated in FIG. 1b, is provided and is appropriately configured to enable electrical access by external test equipment, which in turn supplies an appropriate test voltage across the test structure 150. Moreover, during the sophisticated test conditions 151 and based on the appropriate test voltage, the corresponding induced leakage current is monitored in order to identify a failure in the test structure 150, i.e., a rapid increase of the current.
FIG. 1c schematically illustrates a typical progression of the leakage current obtained through the above-described test procedure. As indicated, a moderately low leakage current may be observed, as long as any modifications of the test structure 150 may not result in a significant modification of the dielectric material 111 and/or the metal lines 112. Usually, a corresponding modification may occur, such as a dielectric breakdown, which may result in a drastic increase of the leakage current, as indicated by the time T0, which may thus be considered as a failure in the test structure 150, thereby also indicating a corresponding weakness of actual metallization systems. Consequently, on the basis of the time T0, the reliability of the test structure 150 and thus of any metal line configuration and manufacturing techniques used for forming the test structure 150 may be evaluated with respect to reliability. However, due to the very complex manufacturing flow, as previously described, a large number of aspects may contribute to the dielectric breakdown which, however, may not be substantially assessed or evaluated on the basis of the test structure 150. That is, typically, the rapid increase of the current during the test procedure described above may result in a catastrophic failure in a corresponding region of the test structure 150, which may result in a rupture of dielectric materials and massive damage so that any further analysis, for instance by cross-sectional analysis and the like, may not provide any valuable information about a failure mechanism. Thus, it would be desirable to shut off test voltage before the leakage current may have exceeded critical values so that a corresponding catastrophic failure may not be induced, thereby allowing, upon detecting a corresponding failure in the test structure 150, further analysis of the corresponding failure region in the structure 150. It turns out, however, that a corresponding increase of the leakage current may occur within very short time intervals, for instance within several nanoseconds, which may be extremely difficult to be detected and evaluated by the external test circuitry.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.